# Try our new SoC tools!

### 21 Dec

Written By [Michelle Blaydon](/content/blog?author=65eaf25915118e2db38661db/index.html)

In our [first tutorial](https://docs.chipflow.io/en/latest/tutorial-intro-chipflow-platform.html) we’re going to show you how easy it can be to define a custom SoC with our tools.

Radiona ULX3S FPGA board

You start out by installing the environment and our demo SoC. After building you can either run a local simulation or try it on an FPGA - we’re currently supporting the awesome [UXL3S from Radiona](https://eu.mouser.com/ProductDetail/Radiona/CS-ULX3S-01?qs=hWgE7mdIu5Sz6R%252BJENFe0A%3D%3D).

After verifying it works, you can go on to add a new button press peripheral, and this is the cool part, because of the Amaranth framework, it’s as easy as adding a few lines:

```
self.btn = GPIOPeripheral(
```

```
    pins=self.load_provider(platform, "ButtonGPIO").add(m)
```

```
)
```

```
self._decoder.add(self.btn.bus, addr=self.btn_gpio_base)
```

Adding a low level C driver is similarly easy, and can be tested with the local simulation or using the buttons shown on the FPGA above.

We’re not quite ready for the final part - targeting silicon, but we hope that this tutorial shows our vision for enabling software engineers to start building custom chips. If you want to know when we launch the silicon tooling, [sign up here](/content/beta/index.html).

[Michelle Blaydon](/content/blog?author=65eaf25915118e2db38661db/index.html)